The expanding world of open-source EDA tools and digital circuit design keeps getting more mature year after year. In the recent years, A lot of open source projects came to light that supports full open-source RTL flows, open-source cores, and many more!
TL-Verilog and its ecosystem has been one of the leading projects in advancing the hardware design by abstracting the RTL design in a higher transaction level between pipelines. The online IDE Makerchip supports visualization of TL-Verilog designs using the support of JS libraries. One of the important benefits of VIZ framework is to help hardware designers to debug their design, by viewing simulation trace data in a visual way. It integrates tightly with TL-Verilog, but works with any design language, as will be shown.
Control and Status Registers are an integral part of many hardware systems and cores. They provide communication between components built and designers. By visualizing their contents and actions, this will help the designer to debug the design easily when they see the live visualized waveform.
Hi, my name is Ali Mohsen. a GSoC 2025 contributor working with The FOSSi Foundation. Combining the innovative TL-Verilog language and its online IDE Makerchip with PeakRDL which is a CSR (control and status registers) automation tool. What I created is a plugin for PeakRDL that generates a visualization for the CSR designs, and renders that using Makerchip’s VIZ framework. Let’s take a dive into each one of these technologies to give you a background on the project!
TL-Verilog is an innovative extension to Verilog that abstracts the RTL design, which makes hardware design much easier, faster and shorter. And what better way to get to know TL-Verilog than from its creator Steve Hoover. Check this blog post and the TL-Verilog introduction.
A TL-Verilog design example in comparison to SystemVerilog